CXD8871Q (1/4) gnd gnd dd v (+5v) dd v (+5v) gnd gnd gnd dd v (+5v) gnd dd v (+5v) gnd gnd 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 - top view - c-mos matrix data processor ********** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 il08
pin no. i/o signal signal i/o no. pin signal i/o no. pin signal i/o no. pin CXD8871Q (2/4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 i/o o ? ? o i/o i/o i/o i i i/o i/o o o ? o o i/o i/o i i i i i/o i/o i/o o ? ? o i/o i/o i/o i i i i i i ? i i i i i i i i i i/o i/o o ? ? o i/o i/o i i i i i/o i/o o ? o i/o i/o i i i i i i i/o i/o o ? ? o i/o i/o i i i i i/o i/o o ? o i/o i/o i i i i i i/o i/o rd02 key0 gnd key1 rd20 rd21 rd22 kms0 kms1 rd03 rd04 key2 key3 key4 key5 rd23 rd24 pam cax cay tsw rd05 rd06 rd07 key6 gnd key7 rd25 rd26 rd27 smh tit0 tit1 tit2 tit3 wenb gnd ck pay0 pay1 pay2 pay3 per0 per1 per2 per3 rd10 rd11 mc00 gnd mc01 rd30 rd31 wd00 wd01 wd02 wd03 rd12 rd13 mc10 gnd mc11 rd32 rd33 wd04 wd05 har sel wd06 wd07 rd14 rd15 mc20 gnd mc21 rd34 rd35 wd10 wd11 wd12 wd13 rd16 rd17 mc30 gnd mc31 rd36 rd37 wd14 wd15 renb wd16 wd17 rd00 rd01 v dd v dd v dd v dd gnd (v =+5v) dd
58 59 60 61 69 70 73 74 83 84 85 86 94 95 97 98 52 55 64 66 77 80 89 91 2 5 13 14 16 17 27 30 mc00 mc01 mc10 mc11 mc20 mc21 mc30 mc31 key0 key1 key2 key3 key4 key5 key6 key7 wd00 wd01 wd02 wd03 wd04 wd05 wd06 wd07 wd17 wd16 wd15 wd14 wd13 wd12 wd11 wd10 input output mc01-mc00 mc11-mc10 mc21-mc20 mc31-mc30 key7-key0 ; block 0 (left upper) matrix data ; block 1 (right upper) matrix data ; block 2 (left lower) matrix data ; block 3 (right lower) matrix data ; linear key for soft edge input/output rd07-rd00, rd17-rd10, rd27-rd20, rd37-rd30 ; read data inputs, write data outputs sel 0 1 rd0 in wd0 out rd1 in wd1 out rd2 wd0 out in rd3 wd1 out in mc & key from rd0, rd1 from rd2, rd3 CXD8871Q (3/4) 42 43 44 45 46 47 48 49 39 72 96 35 36 37 38 23 20 21 22 34 71 9 10 41 pay0 pay1 pay2 pay3 per0 per1 per2 per3 wenb sel renb tit0 tit1 tit2 tit3 tsw pam cax cay smh har kms0 kms1 rd00 rd01 rd02 rd03 rd04 rd05 rd06 rd07 rd17 rd16 rd15 rd14 rd13 rd12 rd11 rd10 rd20 rd21 rd22 rd23 rd24 rd25 rd26 rd27 99 100 11 12 24 25 26 50 51 62 63 75 76 87 88 6 7 8 18 19 31 32 33 1 cax cay cl har kms1, kms0 pam pay3-pay0 per3-per0 renb sel smh tit3-tit0 tsw wd07-wd00 wd17-wd10 wenb ; latch enable for wd0 and wd1 ; write data to memory (match for rd1 and rd3) ; write data to memory (match for rd0 and rd2) ; title switch ; title signals ; matrix set ; read/write switching for i/o buffer ; latch enable for rd0, rd1, rd2 and rd3 ; matrix data operation error data ; matrix data select (4 bit to 2 bit) ; address mode select ; linear key mode select ; matrix set (at smh=h) effective area ; system clock ; y select at counter address mode ; x select at counter address mode l=data set on h level, h=data set on l level 0=ffh, 1=00h, 2=linear key, 3=turn over key l=operator, h=counter h=error, matrix data set to l level l=rd0 and rd1 on read, rd2 and rd3 on write h=rd2 and rd3 on read, rd0 and rd1 on write l=normally operation h=data set on h level h=title (matrix data change 11 to 01) l=title on, h=title off 56 57 67 68 82 93 92 81 rd37 rd36 rd35 rd34 rd33 rd32 rd31 rd30
45-42 -pay0 pay3 4 69,61-58 74,73,70 -wd00 wd07 88 wd17 -wd10 98,97,95 94,86-83 11,1,100,99 26-24,12, -rd00 rd07 8 i/o i/o 8 rd17 -rd10 88,87,76, 75,63,62. i/o 8 rd27 -rd20 33-31,19, 18,8-6 51,50 57,56 81,68,67, 93,92,82, -rd30 rd37 8 i/o 4 per3 -per0 49-46 4 8 8 4 matrix data selector 2 2 22 selector matrix data 2 8 8 8 8 2 39 wenb 72 sel 41 clk 96 renb 2 2 22 4 matrix data processor title data selector 4 tit3 38-35 23 tsw 20 pam 21 cax 22 cay 4 key modifier 8 8 22 2 2 output buffer 10,9 kms1 kms0 -tit0 8 14,13,5,2 30,27,17,16, key7 -key0 mc30 mc31 91,89 2 2 80,77 mc21 mc20 2 66,64 mc11 mc10 2 55,52 mc01 mc00 2 CXD8871Q (4/4) har 71 smh 34
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